The MPEG-2 standard describes an encoding method that results in substantial bandwidth reduction by a subjective lossy compression followed by a lossless compression. The encoded, compressed digital data is subsequently decompressed and decoded in an MPEG-2 compliant decoder. Video decoding in accordance with the MPEG-2 standard is described in detail in commonly assigned U.S. Letters Pat. No. 5,576,765, entitled “Video Decoder”, which is hereby incorporated herein by reference in its entirety.
Video decoders are typically embodied as general or special purpose processors and memory. For a conventional MPEG-2 decoder, two decoded reference frames are typically stored in memory at the same time. Thus, the cost of memory can often dominate the cost of the decode system. For example, an MPEG-2 video decoder might employ 2 MB or more of external memory, which generally comprises Dynamic Random Access Memory (DRAM). External memory is used for various data areas, or buffers such as frame buffers.
In practice, the MPEG-2 video decoder is typically limited to 2 MB of external memory in order to minimize cost of the end product. The decoder must perform all of its functions within this limitation. For example, of particular importance is enabling output for both the European market which utilizes the PAL standard of 576 video scan lines and the U.S. market which utilizes the NTSC standard of 480 video scan lines. Even if there is no 2 MB of external memory limitation, it is advantageous to perform the video decode and display in as small a memory space as possible in order to give the remaining memory to other built-in features, such as on-screen graphics.
The MPEG-2 decompressed video data buffers, also called frame buffers, consume the largest part of external DRAM, therefore they are the prime candidate for memory reduction/compression. The frame buffers contain final pixel display and MPEG-reference data, and hence the reduction technique must also retain high video fidelity.
As the MPEG video decoder market becomes more and more competitive, there is a need for high level of feature integration at the lowest possible cost to achieve success in the marketplace. One such feature that, in the past, would have required circuitry external to the video decoder function is video scaling. The kind of scaling desired is to reduce the size of the display picture by a factor, such as 2 or 4, in both the horizontal and vertical axis.
In view of the above, and in order to establish commercial advantage, a novel design is desired wherein a video scaling feature is built into the video decoder, such that advantageous use of existing decoder hardware can be applied to the processes required to produce a high quality scaled image. In one principal aspect, the present invention addresses this need.